PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

Download
ID 683716
Date 12/13/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.7.1. Implementation using the PHY Lite for Parallel Interfaces IP

You can configure the PHY Lite for Parallel Interfaces IP to support multiple groups (maximum 48 I/O pins each).

The following lists the possible implementations:

  • Instantiates one PHY Lite for Parallel Interfaces IP with two groups
    • Bidirectional type for DQ and DQS signals
    • Output type for Addr/Cmd signals
Note: Each group in the PHY Lite for Parallel Interfaces IP can have 48 I/Os, and the IP supports up to 18 groups.
Figure 94.  General Tab Settings


Figure 95.  Group 0 settings (Bidirectional type for DQ and DQS)


Figure 96.  Group 1 settings (Output type for Addr/Cmd)


Did you find the information on this page useful?

Characters remaining:

Feedback Message