2.2.5. I/O Timing
You are advised to design the system with the worst case losses for the PHY Lite for Parallel Interfaces Intel® Agilex™ FPGA IP.
|Data Flow Direction||Applies to PHY Lite for Parallel Interfaces IP Mode||Worst Case Losses4|
|Driving (PHY Lite for Parallel Interfaces IP is driving the I/Os)||Output / bi-directional||45% UI|
|Receiving (PHY Lite for Parallel Interfaces IP is sampling the I/Os)||Input / bi-directional||
POD 1.2 V: 38% UI
SSTL 1.2 V: 49% UI
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