PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

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ID 683716
Date 12/13/2021
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3.3.2.5. Termination Signals

Table 47.  Termination SignalsThe termination signals are signals that are available when you enable the Expose termination ports parameter. The <n> in the signal names below represents the group number in the IP.
Signal Name Direction Width Description
group_<n>_seriesterminationcontrol Input

16

Connect this signal to the series termination control signal of the OCT Intel® FPGA IP to receive series termination code to calibrate Rs.
group_<n>_parallelterminationcontrol Input

16

Connect this signal to the parallel termination control signal of the OCT Intel® FPGA IP to receive parallel termination code to calibrate Rt.

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