2.4. I/O Standards
The PHY Lite for Parallel Interfaces Intel® Agilex™ FPGA IP allows you to set I/O standards on the pins associated with the generated configuration. The I/O standard controls the available strobe configurations and OCT settings for all groups.
|I/O Standard||Valid Input Terminations (Ω)||Valid Output Terminations (Ω)||RZQ (Ω)|
|SSTL-12||50, 60||34, 40||240|
|1.2-V POD||50, 60||34, 40||240|
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