ID 683716
Date 12/13/2021
Public

3.2.5.2.2. Parameter Table Examples

Single PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP

The following figure shows an example of the design containing a single PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP with one bidirectional group composed of four data bits and one strobe. Refer to the Example of Identifying the Lane and Pin Addresses from Parameter Table to determine the lane and pin addresses from the parameter table.

Figure 41. Parameter Table Example for Intel Stratix 10 Devices
Table 30.  Example of Identifying the Lane and Pin Addresses from Parameter Table
To access the parameter table. Base address 27’h5000000
To determine the size of the parameter table by generating an address Base address + 24’h14 27’h5000000 + 24’h14 = 27’h5000014 0000007C The size of the parameter table is 7C that means the information about PHY Lite is from address 27’h5000000 to 27’h500007C.
To determine the address offset of PHY Lite in parameter table. Base address + 27’h24 27’h5000000 + 27’h24 = 27’h5000024 8000005C
• Bit[1:0]: 5C address offset point to PHY Lite
• Bit[6]: PHY Lite interface ID
• {4’h0, pt_ptr[23:0]} is 5C
To determine the number of groups in PHY Lite for interfaces Base address + {12'h0,pt_ptr[15:0]} + 27'h4 27’h5000000 + 27’h000005C + 27’h4= 27’h5000060 00000001 1 indicates the number of groups in this PHY Lite.
To determine the group information that includes the number of lanes and number of pins Base address + {12'h0,pt_ptr[15:0]} + 28'h8 27’h5000000 + 27’h000005C + 27’h8 = 27’h5000064 00000005
• Bit[5:0]: num_pins[5:0] represents 5 pins
• Bit[7:6]: num_lanes[7:6] represents 1 lane
To determine lane offset and pin offset Base address + {12'h0,pt_ptr[15:0]} + 28'hC 27’h5000000 + 27’h500005C + 28’hC = 27’h5000068 006C0070
• Bit[3:0]: pin_off[15:0] = pin_off = 070
• Bit[7:4]: lane_off[31:16], means lane_off = 06C
• lane_ptr = 06C and pin_ptr= 070

27’h5000000 + 28’h6C = 27’h500006C 00000000 Lane address is 0x00
To determine the pin address at 27’h5000070 to 27’h500007C Base address + + {12'h000,pin_ptr[15:0]} 27’h5000000 + 28’h70 = 27’h5000070 23F123E0
• Bit[3:0]: strobe_io = lane 0x23, pin 0
• Bit[7:4]: data_io[0] = lane 0x23, pin 1
5000074 23F323F2
• Bit[3:0]: data_io[1] = lane 0x23, pin 2
• Bit[7:4]: data_io[2] = lane 0x23, pin 3
5000078 000023F4
• Bit[3:0]: data_io[3] = lane 0x23, pin 4
27’h500007C 00000000 End of the address
Note: {lane_addr[7:0], 0xE, pin[3:0]} for strobe and {lane_addr[7:0], 0xF, pin[3:0]} for data.

Two PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IPs

The following figure shows an example of a design containing two PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IPs, each with one bidirectional group composed of four data bits and one strobe. Both interfaces are in the same I/O column, and therefore must merge the tables.

Figure 42. Parameter Table Example for Intel® Stratix® 10 Devices
Important: There is no guarantee of the ordering of the interface parameter tables in the merged table. You must perform a search to locate a specific interface parameter.