PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 12/13/2021

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents I/O Timing Violation

It can be difficult to achieve timing closure for I/O paths at high frequency. Use the dynamic reconfiguration feature to calibrate the I/O path.