PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

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ID 683716
Date 12/13/2021
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2.2.3.3.1. Input Path Data Alignment

The bus ordering of group_data_to_core, group_rdata_en, and group_rdata_valid is identical to the ordering of the output path. The LSBs of the bus hold the first time slice of data received.

The group_rdata_valid delay is always set by the IP to match the group_rdata_en alignment. For example, quarter-rate delays are multiples of four external memory clock cycles (one quarter rate clock cycle).

Reading from an unaligned memory address is called unaligned reads. Unaligned reads will result in unaligned group_rdata_valid and group_data_to_core with data and valid signals packed to the LSBs. This request causes the IP to do two or more read operations.

The following waveform shows an example of aligned reads on the input path of the PHY Lite for Parallel Interfaces Intel® Agilex™ FPGA IP. At the first rising edge of the core_clk_out signal, the group_0_rdata_en bus shows data of 4'hf, which represents all incoming data are aligned. The group_0_rdata_valid bus shows the data of 4'hf, which represents all incoming data are valid. Therefore, the incoming read data on the group_0_data_to_core bus matches the data seen on the group_0_data_io bus.

Figure 13. Example Input (Quarter Rate DDR) - Aligned


The following waveform shows an example of unaligned reads on the input path of the PHY Lite for Parallel Interfaces Intel® Agilex™ FPGA IP.

The data from an unaligned read operation comes in two phases. At the first rising edge of the core_clk_out signal, the group_0_rdata_en bus shows value of 4'he, which shows there are 6 bytes of incoming data from group_0_data_io bus. On the subsequent clock cycle, the group_0_rdata_en bus shows value of 4'h1, which shows there are 2 bytes of incoming data from group_0_data_io bus.

The valid data are transfer to the IP through the group_0_data_to_core bus. At first rising edge of the core_clk_out signal, group_0_rdata_valid bus shows a value of 4'h7, which represents the first 6 bytes of the data from the group_0_data_to_core bus are valid and the last 2 bytes are invalid. On the subsequent clock cycle, group_0_rdata_valid bus shows the value of 4'h1, which shows the last 2 bytes of the data from the group_0_data_to_core bus are valid.

Figure 14. Example Input (Quarter Rate DDR) - Unaligned


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