18.104.22.168.2. Generate the Simulation Design Example
The make_sim_design.tcl generates a simulation design example and tool specific scripts to compile and elaborate the necessary files.
quartus_sh -t make_sim_design.tcl VERILOG
quartus_sh -t make_sim_design.tcl VHDL
This script generates a sim directory containing one subdirectory for each supported simulation tools. Each subdirectory contains the specific scripts to run simulation using the corresponding tool.
The simulation design example provides an example of the core and I/O connectivity for your IP configuration with Calibration IP as the interface for the Avalon® memory-mapped calibration addresses. The addresses of all the configurable registers are saved in the addr_map.vh file. The IOSSM Tester block sends a simple sequence (write/read to a delay register) as a sample. Functionally, the simulation triggers read and write operations over each group in your configured IP. The following diagrams show a simple one group PHY Lite for Parallel Interfaces Intel® Agilex™ FPGA IP instantiation in the testbench.
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