PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

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ID 683716
Date 12/13/2021
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2.6.1.2.2. Generate the Simulation Design Example

The make_sim_design.tcl generates a simulation design example and tool specific scripts to compile and elaborate the necessary files.

To generate the design example for a Verilog or a mixed-language simulator, run the following script at the end of IP generation:
quartus_sh -t make_sim_design.tcl VERILOG
To generate the design example for a VHDL-only simulator, run the following script:
quartus_sh -t make_sim_design.tcl VHDL

This script generates a sim directory containing one subdirectory for each supported simulation tools. Each subdirectory contains the specific scripts to run simulation using the corresponding tool.

The simulation design example provides an example of the core and I/O connectivity for your IP configuration with Calibration IP as the interface for the Avalon® memory-mapped calibration addresses. The addresses of all the configurable registers are saved in the addr_map.vh file. The IOSSM Tester block sends a simple sequence (write/read to a delay register) as a sample. Functionally, the simulation triggers read and write operations over each group in your configured IP. The following diagrams show a simple one group PHY Lite for Parallel Interfaces Intel® Agilex™ FPGA IP instantiation in the testbench.

Figure 25. Dynamic Reconfiguration Simulation Design Example
Figure 26. Write Operation Using Dynamic Reconfiguration
Figure 27. Read Operation Using Dynamic Reconfiguration

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