18.104.22.168. Timing Components
|Circuit Category||Timing Paths||Source||Destination||Description|
|Source synchronous and optionally calibrated 9||Read Path||Memory Device||DQ Capture Register||Source synchronous timing paths—paths where clock and data signals are passed from the transmitting devices to the receiving devices.
Optionally calibrated paths—paths with delay elements that are dynamically reconfigurable to achieve timing closure, especially at higher frequency, and to maximize the timing margins. You can calibrate these paths by implementing an algorithm and turning on the optional dynamic reconfiguration feature. An example of the calibrated path is the FPGA to memory device write path, in which you can dynamically reconfigure the delay elements to, for instance, compensate the skew due to process voltage temperature variation.
|Source synchronous and optionally calibrated 9||Write Path||FPGA DQ/DQS||Memory Device|
|Internal FPGA||Core to PHY Lite for Parallel Interfaces IP Path||Core Registers||Write FIFO||The internal FPGA paths are paths in the FPGA fabric. The Timing Analyzer reports the corresponding timing margins.|
|Internal FPGA||PHY Lite for Parallel Interfaces IP to Core||Read FIFO||Core Registers|
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