PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 12/13/2021

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4.4.2. On-Chip Termination (OCT)

PHY Lite for Parallel Interfaces IP provides valid OCT settings for each group (refer to the I/O Standards topic for supported termination values). These settings are written to the .qip of the instance during generation. If you select an I/O standard that supports OCT in the General tab, you can use the OCT blocks provided in the Intel® Arria® 10 and Intel® Cyclone® 10 GX devices.

You can instantiate the OCT block in one of two ways:

  • Using RZQ_GROUP assignment in the assignment editor, or
  • Manual insertion of OCT block

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