AN 888: PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Stratix® 10 Devices

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ID 683220
Date 9/11/2020
Public
Document Table of Contents
Document Table of Contents x
1. PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Stratix® 10 Devices
1. PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Stratix® 10 Devices x
1.1. Features 1.2. Hardware and Software Requirements 1.3. Design System Architecture Overview 1.4. Dynamic Reconfiguration Overview 1.5. PHY Lite Per-Bit Overview 1.6. Compiling the Reference Design 1.7. Hardware Testing 1.8. Document Revision History for AN 888: PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Stratix® 10 Devices 1.9. Appendix A: HiLo Loopback Card Pin Connections 1.10. Appendix B: Retrieving Lane and Pin Information 1.11. Appendix C: Decoding Parameter Table
1.3. Design System Architecture Overview x
1.3.1. Functional Description
1.3.1. Functional Description x
1.3.1.1. DUT_MODULE 1.3.1.2. Traffic Generator/Checker Module 1.3.1.3. DYN_CFG Controller 1.3.1.4. Clocking Scheme
1.4. Dynamic Reconfiguration Overview x
1.4.1. Register Address Map 1.4.2. Dynamic Reconfiguration API Functions
1.5. PHY Lite Per-Bit Overview x
1.5.1. Per-Bit Deskew Concept 1.5.2. Read Deskew Algorithm
1.7. Hardware Testing x
1.7.1. Setting Up the Development Kit 1.7.2. Generating Executable and Linking Format (.elf) Programming File 1.7.3. Running the Hardware Reference Design 1.7.4. Results
1.7.4. Results x
1.7.4.1. Dynamic Calibration Result 1.7.4.2. Random Data Transfer Result
1. PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Stratix® 10 Devices

1.11. Appendix C: Decoding Parameter Table

Figure 23. Parameter Table Example for Intel® Stratix® 10 Devices
Notes to Figure 23:
  1. To access the parameter table = 27’h5000000
  2. To determine the size of the parameter table, generate an address. For example:
    addr = 27’h5000000 + 24’h14
value at addr = 0xAC

    The size of parameter table is AC, which means that information about the PHY Lite for Parallel Interfaces IP cores are spread from address 27’h5000000 to 27’h50000AC .

  3. To determine the address offset of the PHY Lite for Parallel Interfaces IP cores in the parameter table.
    • There are two PHY Lite for Parallel Interfaces IP cores in the parameter table at address offset. For example:
      27’h5000024 = 8200005C
27’h5000028 = 83000084

      where 0x5C address offset points to PHY Lite for Parallel Interfaces IP core 1 and 0x84 address offset points to PHY Lite for Parallel Interfaces IP core 2.

    • 2 and 3 (marked in yellow box) are the PHY Lite for Parallel Interfaces IP core interface IDs.
  4. To determine the number of groups in the PHY Lite for Parallel Interfaces IP core interfaces :
    27’h5000060 = 00000001

    The underlined number indicates that there is only one group.

  5. To determine the group information (for example, the number of lanes and pins in a PHY Lite for Parallel Interfaces IP core interface): 
    27’h5000064 = 0000000A
    where num_lanes[7:6],num_pins[5:0] means lanes = 1 and pins = 10.
  6. To determine the lane and pin address offsets: 
    27’h5000068 = 006C0070
    where lane_off[31:16],pin_off[15:0] means lane off = 0x6C and pin off = 0x70.
  7. To determine the lane address: 
    27’h500006C = 00000053
    where the lane address is 0x53.
  8. To determine the pin address at 27’h5000070 to 27’h5000080 : 
    27’h5000070 = 53E553E4
    where
    • DQS_P = Pin 4; DQS_N = Pin 5
    • DQ[0] = Pin 9; DQ[1] = Pin 6
    • DQ[2] = Pin 8; DQ[3] = Pin A
    • DQ[4] = Pin B; DQ[5] = Pin 7
    • DQ[6] = Pin 3; DQ[7] = Pin 1
    Note: {lane_addr[7:0],0xE,pin[3:0]} for strobe and {lane_addr[7:0],0xF,pin[3:0]} for data.
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