AN 888: PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Stratix® 10 Devices

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ID 683220
Date 9/11/2020
Public
Document Table of Contents
Document Table of Contents x
1. PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Stratix® 10 Devices
1. PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Stratix® 10 Devices x
1.1. Features 1.2. Hardware and Software Requirements 1.3. Design System Architecture Overview 1.4. Dynamic Reconfiguration Overview 1.5. PHY Lite Per-Bit Overview 1.6. Compiling the Reference Design 1.7. Hardware Testing 1.8. Document Revision History for AN 888: PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Stratix® 10 Devices 1.9. Appendix A: HiLo Loopback Card Pin Connections 1.10. Appendix B: Retrieving Lane and Pin Information 1.11. Appendix C: Decoding Parameter Table
1.3. Design System Architecture Overview x
1.3.1. Functional Description
1.3.1. Functional Description x
1.3.1.1. DUT_MODULE 1.3.1.2. Traffic Generator/Checker Module 1.3.1.3. DYN_CFG Controller 1.3.1.4. Clocking Scheme
1.4. Dynamic Reconfiguration Overview x
1.4.1. Register Address Map 1.4.2. Dynamic Reconfiguration API Functions
1.5. PHY Lite Per-Bit Overview x
1.5.1. Per-Bit Deskew Concept 1.5.2. Read Deskew Algorithm
1.7. Hardware Testing x
1.7.1. Setting Up the Development Kit 1.7.2. Generating Executable and Linking Format (.elf) Programming File 1.7.3. Running the Hardware Reference Design 1.7.4. Results
1.7.4. Results x
1.7.4.1. Dynamic Calibration Result 1.7.4.2. Random Data Transfer Result
1. PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Stratix® 10 Devices

1.4.2. Dynamic Reconfiguration API Functions

Table 1.  Dynamic Reconfiguration API Functions
API Function Access Type

(R/W)

 Argument Return Value Description
Read_Param_table R N/A Parameter contents Retrieve parameter table contents from the I/O SSM memory.
get_output_delay R
  • ID
  • NUM_GROUP
  • PIN
  • CSR
 DELAY value Read from the PIN_OUTPUT_DELAY register for the specified ID, group number, and pin number.
Specified CSR to:
  • 0 to read from Avalon® register.
  • 1 to read from CSR register.
get_data_input_delay R
  • ID
  • NUM_GROUP
  • PIN
 DELAY value Read from the PIN_INPUT_DELAY register for the specified ID, group number, and pin number.
get_strobe_input_delay R
  • ID
  • NUM_GROUP
 DELAY value Read from the STROBE_INPUT_DELAY register for the specified ID and group number.
get_strobe_enable_delay R
  • ID
  • NUM_GROUP
  • CSR
 DELAY value Read from the STROBE_EN_DELAY register for the specified ID and group number.
Specified CSR to:
  • 0 to read from Avalon® register.
  • 1 to read from CSR register.
get_strobe_enable_phase R
  • ID
  • NUM_GROUP
  • PIN
 DELAY value Read from the READ_EN_PHASE register for the specified ID and group number.
Specified CSR to:
  • 0 to read from Avalon® register.
  • 1 to read from CSR register.
get_read_valid_delay R
  • ID
  • NUM_GROUP
  • PIN
 DELAY value Read from the READ_VALID_DELAY register for the specified ID and group number.
Specified CSR to:
  • 0 to read from Avalon® register.
  • 1 to read from CSR register.
set_output_delay W
  • ID
  • NUM_GROUP
  • PIN
  • DELAY value
 N/A Write to PIN_OUTPUT_DELAY register for the specified ID, group number, and pin number.
set_data_input_delay W
  • ID
  • NUM_GROUP
  • PIN
  • DELAY value
 N/A Write to PIN_INPUT_DELAY register for the specified ID, group number, and pin number.
set_strobe_input_delay W
  • ID
  • NUM_GROUP
  • PIN
  • DELAY value
 N/A Write to STROBE_INPUT_DELAY register for the specified ID and group number.
set_strobe_enable_delay W
  • ID
  • NUM_GROUP
  • PIN
  • DELAY value
 N/A Write to STROBE_ENABLE_DELAY register for the specified ID and group number.
set_strobe_enable_phase W
  • ID
  • NUM_GROUP
  • PIN
  • DELAY value
 N/A Write to STROBE_ENABLE_PHASE register for the specified ID and group number.
set_read_valid_delay W
  • ID
  • NUM_GROUP
  • PIN
  • DELAY value
 N/A Write to READ_VALID_DELAY register for the specified ID and group number.
Notes to Table 1:
  1. ID—Interface ID set during PHY Lite for Parallel Interfaces instantiation.
  2. NUM_GROUP—The number of data/strobe groups in the interface.
  3. PIN—Logical pin of the interface.
  4. DELAY value—Refer to Control Registers Description section of the PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide.
Related Information
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