AN 888: PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Stratix® 10 Devices

ID 683220
Date 9/11/2020
Public
Document Table of Contents

1.4.2. Dynamic Reconfiguration API Functions

Table 1.  Dynamic Reconfiguration API Functions
API Function Access Type

(R/W)

Argument Return Value Description
Read_Param_table R N/A Parameter contents Retrieve parameter table contents from the I/O SSM memory.
get_output_delay R
  • ID
  • NUM_GROUP
  • PIN
  • CSR
DELAY value Read from the PIN_OUTPUT_DELAY register for the specified ID, group number, and pin number.
Specified CSR to:
  • 0 to read from Avalon® register.
  • 1 to read from CSR register.
get_data_input_delay R
  • ID
  • NUM_GROUP
  • PIN
DELAY value Read from the PIN_INPUT_DELAY register for the specified ID, group number, and pin number.
get_strobe_input_delay R
  • ID
  • NUM_GROUP
DELAY value Read from the STROBE_INPUT_DELAY register for the specified ID and group number.
get_strobe_enable_delay R
  • ID
  • NUM_GROUP
  • CSR
DELAY value Read from the STROBE_EN_DELAY register for the specified ID and group number.
Specified CSR to:
  • 0 to read from Avalon® register.
  • 1 to read from CSR register.
get_strobe_enable_phase R
  • ID
  • NUM_GROUP
  • PIN
DELAY value Read from the READ_EN_PHASE register for the specified ID and group number.
Specified CSR to:
  • 0 to read from Avalon® register.
  • 1 to read from CSR register.
get_read_valid_delay R
  • ID
  • NUM_GROUP
  • PIN
DELAY value Read from the READ_VALID_DELAY register for the specified ID and group number.
Specified CSR to:
  • 0 to read from Avalon® register.
  • 1 to read from CSR register.
set_output_delay W
  • ID
  • NUM_GROUP
  • PIN
  • DELAY value
N/A Write to PIN_OUTPUT_DELAY register for the specified ID, group number, and pin number.
set_data_input_delay W
  • ID
  • NUM_GROUP
  • PIN
  • DELAY value
N/A Write to PIN_INPUT_DELAY register for the specified ID, group number, and pin number.
set_strobe_input_delay W
  • ID
  • NUM_GROUP
  • PIN
  • DELAY value
N/A Write to STROBE_INPUT_DELAY register for the specified ID and group number.
set_strobe_enable_delay W
  • ID
  • NUM_GROUP
  • PIN
  • DELAY value
N/A Write to STROBE_ENABLE_DELAY register for the specified ID and group number.
set_strobe_enable_phase W
  • ID
  • NUM_GROUP
  • PIN
  • DELAY value
N/A Write to STROBE_ENABLE_PHASE register for the specified ID and group number.
set_read_valid_delay W
  • ID
  • NUM_GROUP
  • PIN
  • DELAY value
N/A Write to READ_VALID_DELAY register for the specified ID and group number.
Notes to Table 1:
  1. ID—Interface ID set during PHY Lite for Parallel Interfaces instantiation.
  2. NUM_GROUP—The number of data/strobe groups in the interface.
  3. PIN—Logical pin of the interface.
  4. DELAY value—Refer to Control Registers Description section of the PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide.