AN 888: PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Stratix® 10 Devices

ID 683220
Date 9/11/2020
Document Table of Contents

1.5.1. Per-Bit Deskew Concept

In real-life cases, the time DQ signal reaches the receiving side varies, depending on board skew, trace length mismatch, unit variation, and so on. All these factors may result a narrower DQ window than expected, as shown in the following figure:
Figure 5. Passing Window Result Before Per-Bit DeskewThis figure shows data are skewed due to board trace different and other factors, resulting a smaller passing window.

To overcome this, the PHY Lite for Parallel Interfaces IP core has the capability to calibrate each DQ/DQS pin separately. Successful per-bit calibration may improve the total DQS opening window. An example of the per-bit calibration (happening on the RX side) is shown in the following figures:

Figure 6. First DQ_0 Calibrated
Figure 7. Second DQ_1 Calibrated
Figure 8. Comparison of Passing Window Result Before and After Per-Bit Deskew