PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

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ID 683716
Date 6/21/2022
Public
Document Table of Contents

2.2.4.2.2. Control Registers

When you generate a read operation to the control registers addresses, the Avalon® interface returns a set of values from the control registers.

Table 9.  Control Register Bit DescriptionThis table shows the definition of the bits for each control register.
Feature Bit Description
Pin Output Delay [31:13] Reserved.
[12:0]

Phase value.

  • Strobe minimum setting: Refer to the Output and Strobe Enable Minimum and Maximum Phase Settings topic.
  • Strobe maximum setting: Refer to the Output and Strobe Enable Minimum and Maximum Phase Settings topic.
  • Incremental delay: 1/128th VCO clock period.

The CSR value for DQS is set through the Output Strobe Phase parameter during IP instantiation.

Note: The pin output delay switches from the CSR register value to the Avalon® register value after the first Avalon® write. The delay is only reset to the CSR register value on a reset of the interface.
Pin Input Delay [31:13] Reserved.
[12]

Enable bit to select access to Avalon® register or CSR register.

  • 0 = Delay value is 0. CSR register is not available for this feature.
  • 1 = Select delay value from Avalon® register.
[11:9] Reserved.
[8:0]

Delay value.

  • Minimum setting: 0
  • Maximum setting: 511 steps
  • Incremental delay: 1/256th VCO clock period
Strobe Input Delay [31:13] Reserved.
[12]

Enable bit to select access to Avalon® register or CSR register.

  • 0 = Delay value is 0. CSR register is not available for this feature.
  • 1 = Select delay value from Avalon® register.

Modifying these values must be done on all lanes in a group.

[11:10] Reserved.
[9:0]
  • Minimum setting: 0
  • Maximum setting: 1023 steps
  • Incremental Delay: 1/256th VCO clock period

Modifying these values must be done on all lanes in a group.

Strobe Enable Phase [31:13] Reserved.
[12]

Enable bit to select access to Avalon® register or CSR register.

  • 0 = Select delay value from CSR register. The CSR value is set through the Capture Strobe Phase Shift parameter during IP instantiation.
  • 1 = Select delay value from Avalon® register.

Modifying these values must be done on all lanes in a group.

[11:10] Reserved.
[9:0]
  • Minimum setting: 0
  • Maximum setting: 1023 steps
  • Incremental delay: 1/256th VCO clock period

Modifying these values must be done on all lanes in a group.

Strobe Enable Delay [31:16] Reserved.
[15]

Enable bit to select access to Avalon® register or CSR register.

  • 0 = Select delay value from CSR register
  • 1 = Select delay value from Avalon® register

Modifying these values must be done on all lanes in a group.

[14:6] Reserved.
[5:0]

Delay value.

  • Minimum setting: 0 external clock cycles
  • Maximum setting: 63 external memory clock cycles
  • Incremental delay: 1 external memory clock cycle

Modifying these values must be done on all lanes in a group.

Read Valid Delay [31:16] Reserved
[15]

Enable bit to select access to Avalon® register or CSR register.

  • 0 = Select delay value from CSR register
  • 1 = Select delay value from Avalon® register

Modifying these values must be done on all lanes in a group.

[14:7] Reserved.
[6:0]

Delay value.

  • Minimum setting: 0 external clock cycles
  • Maximum setting: 127 external memory clock cycles
  • Incremental delay: 1 external memory clock cycle

Modifying these values must be done on all lanes in a group.

Example Structure of Address Map (addr_map.vh)

This example shows the address value, mask value, delay field offset, and delay field width of an address map (addr_map.vh file). The address value is generated based on information in the Control Register Addresses Description table. The mask value is to be masked with the 32-bit data register pin output delay in the Control Data Register Bit Description table. The delay width of value 13 corresponds to bit 12 to bit 0 for pin output delay in the Control Data Register Bit Description table.

Figure 12. Example Structure of Address Map

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