PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

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ID 683716
Date 6/21/2022
Public
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4.2.5. Dynamic Reconfiguration

Because of the asynchronous nature of the PHY, you must perform calibration to achieve timing closure at a high frequency. At a high level, calibration involves reconfiguring input and output delays in the PHY to align data and strobes. With the PHY Lite for Parallel Interfaces IP, you can perform the calibration by using dynamic reconfiguration feature. The dynamic reconfiguration feature allows you to modify these delays by writing to a set of control registers using an Avalon memory-mapped interface.

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