PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

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Date 6/21/2022
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Document Table of Contents
Document Table of Contents x
1. About the PHY Lite for Parallel Interfaces IP 2. PHY Lite for Parallel Interfaces Intel Agilex FPGA IP 3. PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP 4. PHY Lite for Parallel Interfaces Intel Arria 10 and Intel Cyclone 10 GX FPGA IPs 5. PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide Document Archives 6. Document Revision History for the PHY Lite for Parallel Interfaces IP User Guide
1. About the PHY Lite for Parallel Interfaces IP x
1.1. Device Family Support 1.2. Features
2. PHY Lite for Parallel Interfaces Intel Agilex FPGA IP x
2.1. Release Information 2.2. Functional Description 2.3. Getting Started 2.4. I/O Standards 2.5. Design Guidelines 2.6. Design Example
2.2. Functional Description x
2.2.1. Intel® Agilex™ I/O Sub-bank Interconnects 2.2.2. Intel® Agilex™ Input DQS/Strobe Tree 2.2.3. PHY Lite for Parallel Interfaces Intel® Agilex™ FPGA IP Top Level Interfaces 2.2.4. Dynamic Reconfiguration 2.2.5. I/O Timing
2.2.3. PHY Lite for Parallel Interfaces Intel® Agilex™ FPGA IP Top Level Interfaces x
2.2.3.1. Clocks 2.2.3.2. Output Path 2.2.3.3. Input Path
2.2.3.1. Clocks x
2.2.3.1.1. Clock Frequency Relationships
2.2.4. Dynamic Reconfiguration x
2.2.4.1. Connectivity 2.2.4.2. Reconfiguration Features and Register Addressing 2.2.4.3. Dynamic Reconfiguration Guidelines
2.2.4.2. Reconfiguration Features and Register Addressing x
2.2.4.2.1. Control Registers Addresses 2.2.4.2.2. Control Registers
2.2.4.3. Dynamic Reconfiguration Guidelines x
2.2.4.3.1. Strobe Enable Window Calibration 2.2.4.3.2. Output and Strobe Enable Minimum and Maximum Phase Settings 2.2.4.3.3. Input DQ/DQS Delay Chains Maximum Values
2.3. Getting Started x
2.3.1. Parameter Settings 2.3.2. Signals
2.3.1. Parameter Settings x
2.3.1.1. Read Latency 2.3.1.2. Write Latency
2.3.2. Signals x
2.3.2.1. Clock and Reset Interface Signals 2.3.2.2. Output Path Signals 2.3.2.3. Input Path Signals
2.4. I/O Standards x
2.4.1. Input Buffer Reference Voltage (VREF) 2.4.2. On-Chip Termination (OCT)
2.4.2. On-Chip Termination (OCT) x
2.4.2.1. RZQ_GROUP Assignment
2.5. Design Guidelines x
2.5.1. Guidelines: Group Pin Placement 2.5.2. Reference Clock 2.5.3. Reset
2.6. Design Example x
2.6.1. Generate the Design Example
2.6.1. Generate the Design Example x
2.6.1.1. Design Example without Dynamic Reconfiguration 2.6.1.2. Dynamic Reconfiguration Design Examples
2.6.1.1. Design Example without Dynamic Reconfiguration x
2.6.1.1.1. Generate the Synthesis Design Example 2.6.1.1.2. Generate the Simulation Design Example
2.6.1.2. Dynamic Reconfiguration Design Examples x
2.6.1.2.1. Generate the Synthesis Design Example 2.6.1.2.2. Generate the Simulation Design Example
3. PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP x
3.1. Release Information 3.2. Functional Description 3.3. Getting Started 3.4. I/O Standards 3.5. Design Guidelines 3.6. Design Example
3.2. Functional Description x
3.2.1. Top Level Interfaces 3.2.2. Clocks 3.2.3. Output Path 3.2.4. Input Path 3.2.5. Dynamic Reconfiguration
3.2.2. Clocks x
3.2.2.1. Clock Frequency Relationships
3.2.3. Output Path x
3.2.3.1. Output Path Data Alignment
3.2.4. Input Path x
3.2.4.1. Input Path Data Alignment
3.2.5. Dynamic Reconfiguration x
3.2.5.1. RTL Connectivity 3.2.5.2. Address Lookup 3.2.5.3. Reconfiguration Features and Register Addressing 3.2.5.4. Calibration Guidelines
3.2.5.1. RTL Connectivity x
3.2.5.1.1. Daisy Chain
3.2.5.2. Address Lookup x
3.2.5.2.1. Strobes 3.2.5.2.2. Parameter Table Examples
3.2.5.3. Reconfiguration Features and Register Addressing x
3.2.5.3.1. PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP Control Registers Addresses 3.2.5.3.2. Control Registers Description
3.2.5.4. Calibration Guidelines x
3.2.5.4.1. Strobe Enable Window Calibration 3.2.5.4.2. Output and Strobe Enable Minimum and Maximum Phase Settings
3.3. Getting Started x
3.3.1. Parameter Settings 3.3.2. Signals
3.3.1. Parameter Settings x
3.3.1.1. Read Latency 3.3.1.2. Write Latency
3.3.2. Signals x
3.3.2.1. Clock and Reset Interface Signals 3.3.2.2. Output Path Signals 3.3.2.3. Input Path Signals 3.3.2.4. Avalon Configuration Bus Interface Signals 3.3.2.5. Termination Signals
3.4. I/O Standards x
3.4.1. Input Buffer Reference Voltage (VREF) 3.4.2. On-Chip Termination (OCT)
3.4.1. Input Buffer Reference Voltage (VREF) x
3.4.1.1. Calibrated VREF Settings
3.4.2. On-Chip Termination (OCT) x
3.4.2.1. RZQ_GROUP Assignment 3.4.2.2. Manual Insertion of OCT Block
3.5. Design Guidelines x
3.5.1. Guidelines: Group Pin Placement 3.5.2. Reference Clock 3.5.3. Reset 3.5.4. Constraining Multiple PHY Lite for Parallel Interfaces to One I/O Bank 3.5.5. Dynamic Reconfiguration 3.5.6. Timing
3.5.6. Timing x
3.5.6.1. Timing Components 3.5.6.2. Timing Constraints and Files 3.5.6.3. Timing Analysis 3.5.6.4. Timing Closure Guidelines
3.5.6.2. Timing Constraints and Files x
3.5.6.2.1. <variation_name>.sdc 3.5.6.2.2. <variation_name>_parameter.tcl 3.5.6.2.3. <variation_name>_ip_parameters.tcl 3.5.6.2.4. <variation_name>_pin_map.tcl 3.5.6.2.5. <variation_name>_report_timing.tcl 3.5.6.2.6. <variation_name>_report_timing_core.tcl
3.5.6.4. Timing Closure Guidelines x
3.5.6.4.1. Timing Closure: Dynamic Reconfiguration 3.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints 3.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints 3.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data 3.5.6.4.5. I/O Timing Violation 3.5.6.4.6. Internal FPGA Path Timing Violation
3.6. Design Example x
3.6.1. Generate the Design Example
3.6.1. Generate the Design Example x
3.6.1.1. Design Example without Dynamic Reconfiguration 3.6.1.2. Dynamic Reconfiguration Design Examples
3.6.1.1. Design Example without Dynamic Reconfiguration x
3.6.1.1.1. Generate the Hardware Design Example 3.6.1.1.2. Generate the Simulation Design Example
3.6.1.2. Dynamic Reconfiguration Design Examples x
3.6.1.2.1. Dynamic Reconfiguration Using Finite State Machine
4. PHY Lite for Parallel Interfaces Intel Arria 10 and Intel Cyclone 10 GX FPGA IPs x
4.1. Release Information 4.2. Functional Description 4.3. Getting Started 4.4. I/O Standards 4.5. Design Guidelines 4.6. Design Example 4.7. Application Specific Design Example
4.2. Functional Description x
4.2.1. Top Level Interfaces 4.2.2. Clocks 4.2.3. Output Path 4.2.4. Input Path 4.2.5. Dynamic Reconfiguration
4.2.2. Clocks x
4.2.2.1. Clock Frequency Relationships
4.2.3. Output Path x
4.2.3.1. Output Path Data Alignment
4.2.4. Input Path x
4.2.4.1. Input Path Data Alignment
4.2.5. Dynamic Reconfiguration x
4.2.5.1. RTL Connectivity 4.2.5.2. Address Lookup 4.2.5.3. Reconfiguration Features and Register Addressing 4.2.5.4. Calibration Guidelines
4.2.5.1. RTL Connectivity x
4.2.5.1.1. Daisy Chain
4.2.5.2. Address Lookup x
4.2.5.2.1. Strobes 4.2.5.2.2. Parameter Table Examples
4.2.5.3. Reconfiguration Features and Register Addressing x
4.2.5.3.1. PHY Lite for Parallel Interfaces Intel Arria 10 FPGA IP and PHY Lite for Parallel Interfaces Intel Cyclone 10 GX IPs Address Registers 4.2.5.3.2. Control Registers Description
4.2.5.4. Calibration Guidelines x
4.2.5.4.1. Strobe Enable Window Calibration 4.2.5.4.2. Output and Strobe Enable Minimum and Maximum Phase Settings
4.3. Getting Started x
4.3.1. Parameter Settings 4.3.2. Signals
4.3.1. Parameter Settings x
4.3.1.1. Read Latency 4.3.1.2. Write Latency
4.3.2. Signals x
4.3.2.1. Clock and Reset Interface Signals 4.3.2.2. Output Path Signals 4.3.2.3. Input Path Signals 4.3.2.4. Avalon Configuration Bus Interface Signals 4.3.2.5. Termination Signals
4.4. I/O Standards x
4.4.1. Input Buffer Reference Voltage (VREF) 4.4.2. On-Chip Termination (OCT)
4.4.1. Input Buffer Reference Voltage (VREF) x
4.4.1.1. Calibrated VREF Settings
4.4.2. On-Chip Termination (OCT) x
4.4.2.1. RZQ_GROUP Assignment 4.4.2.2. Manual Insertion of OCT Block
4.5. Design Guidelines x
4.5.1. Guidelines: Group Pin Placement 4.5.2. Reference Clock 4.5.3. Reset 4.5.4. Constraining Multiple PHY Lite for Parallel Interfaces to One I/O Bank 4.5.5. Dynamic Reconfiguration 4.5.6. Timing
4.5.6. Timing x
4.5.6.1. Timing Components 4.5.6.2. Timing Constraints and Files 4.5.6.3. Timing Analysis 4.5.6.4. Timing Closure Guidelines
4.5.6.2. Timing Constraints and Files x
4.5.6.2.1. <variation_name>.sdc 4.5.6.2.2. <variation_name>_parameter.tcl 4.5.6.2.3. <variation_name>_ip_parameters.tcl 4.5.6.2.4. <variation_name>_pin_map.tcl 4.5.6.2.5. <variation_name>_report_timing.tcl 4.5.6.2.6. <variation_name>_report_timing_core.tcl
4.5.6.4. Timing Closure Guidelines x
4.5.6.4.1. Timing Closure: Dynamic Reconfiguration 4.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints 4.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints 4.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data 4.5.6.4.5. I/O Timing Violation 4.5.6.4.6. Internal FPGA Path Timing Violation
4.6. Design Example x
4.6.1. Generate the Design Example
4.6.1. Generate the Design Example x
4.6.1.1. Design Example without Dynamic Reconfiguration 4.6.1.2. Dynamic Reconfiguration Design Examples
4.6.1.1. Design Example without Dynamic Reconfiguration x
4.6.1.1.1. Generate the Hardware Design Example 4.6.1.1.2. Generate the Simulation Design Example
4.6.1.2. Dynamic Reconfiguration Design Examples x
4.6.1.2.1. Dynamic Reconfiguration with Debug Kit 4.6.1.2.2. Dynamic Reconfiguration Using Finite State Machine
4.7. Application Specific Design Example x
4.7.1. Implementation using the PHY Lite for Parallel Interfaces IP
1. About the PHY Lite for Parallel Interfaces IP
2. PHY Lite for Parallel Interfaces Intel Agilex FPGA IP
3. PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP
4. PHY Lite for Parallel Interfaces Intel Arria 10 and Intel Cyclone 10 GX FPGA IPs
5. PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide Document Archives
6. Document Revision History for the PHY Lite for Parallel Interfaces IP User Guide

3.2.5.3.2. Control Registers Description

When you generate a read operation to the control registers addresses, the Avalon interface returns a set of values from the control registers. The following tables show the definition of the bits for each control register.
Table 37.  Control Register Description
Feature Bit Description
Pin Output Delay [31:13]

Reserved 8

[12:0]

Phase value

Strobe minimum setting: Refer to the Output and Strobe Enable Minimum and Maximum Phase Settings topic.

Strobe maximum setting: Refer to the Output and Strobe Enable Minimum and Maximum Phase Settings topic.

Incremental Delay: 1/128th VCO clock period

The CSR value for DQS is set through the Output Strobe Phase parameter during IP instantiation.

Note: The pin output delay switches from the CSR register value to the Avalon register value after the first Avalon write. It is only reset to the CSR register value on a reset of the interface.
Pin Input Delay [31:13]

Reserved 8

[12]

Enable bit to select access to Avalon register or CSR register.

0 = Delay value is 0. CSR register is not available for this feature.

1 = Select delay value from Avalon register
[11:9] Reserved 8
[8:0]

Delay value

Minimum Setting: 0

Maximum Setting: 511 VCO clock periods

Incremental Delay: 1/256th VCO clock period

Strobe Input Delay [31:13]

Reserved 8

[12]

Enable bit to select access to Avalon register or CSR register.

0 = Delay value is 0. CSR register is not available for this feature.

1 = Select delay value from Avalon register

Modifying these values must be done on all lanes in a group.
[11:10] Reserved8
[9:0]

Delay value

Minimum Setting: 0

Maximum Setting: 1023 VCO clock periods

Incremental Delay: 1/256th VCO clock period

Modifying these values must be done on all lanes in a group.
Strobe Enable Phase [31:16] Reserved 8
[15]

Enable bit to select access to Avalon register or CSR register.

0 = Select delay value from CSR register. The CSR value is set through the Capture Strobe Phase Shift parameter during IP instantiation.

1 = Select delay value from Avalon register

Modifying these values must be done on all lanes in a group.
[14:13] Reserved8
[12:0]

Bit [12:0]: Phase value

Minimum Setting: Refer to the Output and Strobe Enable Minimum and Maximum Phase Settings topic.

Maximum Setting: Refer to the Output and Strobe Enable Minimum and Maximum Phase Settings topic.

Incremental Delay: 1/128th VCO clock period

Modifying these values must be done on all lanes in a group.
Strobe Enable Delay [31:16] Reserved8
[15]

Enable bit to select access to Avalon register or CSR register.

0 = Select delay value from CSR register

1 = Select delay value from Avalon register

Modifying these values must be done on all lanes in a group.
[14:6] Reserved8
[5:0]

Delay value

Minimum Setting: 0 external clock cycles

Maximum Setting: 63 external memory clock cycles

Incremental Delay: 1 external memory clock cycle

Modifying these values must be done on all lanes in a group.
Read Valid Delay [31:16] Reserved8
[15]

Enable bit to select access to Avalon register or CSR register.

0 = Select delay value from CSR register

1 = Select delay value from Avalon register

Modifying these values must be done on all lanes in a group.
[14:7] Reserved
[6:0]

Delay value

Minimum Setting: 0 external clock cycles

Maximum Setting: 127 external memory clock cycles

Incremental Delay: 1 external memory clock cycle

Modifying these values must be done on all lanes in a group.
Important: For more information about performing various clocking and delay calculations, depending on the interface frequency and rate, refer to PHYLite_delay_calculations.xlsx.
Related Information

Example of Accessing Dynamic Reconfiguration Control Registers using Parameter Table

The example shows the steps to access Pin Output Delay CSR control register for a strobe pin with the following PHY Lite for Parallel Interfaces IP settings in Intel® Stratix® 10 devices:
  • Number of groups: 2. The group index is automatically set to 0x00.
  • Interface ID: 0x00
  • Pin width: 4
  • Strobe configuration: Single ended
  • Avalon controller calibration bus base address: 0x3000000
After the project compilation, the interface ID, lane address and pin addresses are stored in the parameter table.
The Pin Output Delay CSR control register has the following bit definition:
Bit Description Avalon® MM Register Value
[30:27] Specify the PHY Lite for Parallel Interfaces IP interface ID.

0x00 (Interface ID from parameter table)
[26:24] Specify the Avalon controller calibration bus base address. 0x3
[23:21] Reserved 0x00
[20:13] Specify the lane address of an interface. This value is depending on the resource fitting process during compilation. 0x4b (Lane address from parameter table)
[12:8] Specify the address for the physical location of a pin within a lane. 0x04 (Strobe pin address from parameter table)
[7:0] Reserved 0xe8
To read the Pin Output Delay CSR control register for a strobe pin, use the command 
avl_in_address[30:0] = {interface id[30:27], calibration bus address[26:24], Reserved[23:21], lanes address[20:13], pin address[12:8], reserved[7:0]}
avl_in_address[30:0] = {0x00, 0x3, 0x00, 0x4B, 0x04, 0xE8}
8 Reserved bit ranges must be zero
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