PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

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ID 683716
Date 6/21/2022
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4.2.5.3.1. PHY Lite for Parallel Interfaces Intel Arria 10 FPGA IP and PHY Lite for Parallel Interfaces Intel Cyclone 10 GX IPs Address Registers

The following tables show the register bits to construct the control register addresses for each feature.
Table 67.  Address Register for Pin Output Delay Feature
Bit Description Avalon® MM Register CSR Register
Value Access Type Value Access Type
[31:28] Reserved 4'h0 RW 4'h0 RO
[27:24] Specify the PHY Lite for Parallel Interfaces IP interface ID.

Depending on the Interface ID parameter in the Parameter Editor.

RW

Depending on the Interface ID parameter in the Parameter Editor.

RO
[23:21] Specify the Avalon controller calibration bus base address. 3'h4 RW 3'h4 RO
[20:13] Specify the lane address of an interface. This value is depending on the resource fitting process during compilation. You can query this in the Parameter Table Lookup Operation Sequence as described in the Address Lookup topic. RW You can query this in the Parameter Table Lookup Operation Sequence as described in the Address Lookup topic. RO
[12:8] Specify the address for the physical location of a pin within a lane. You can query this in the Parameter Table Lookup Operation Sequence as described in the Address Lookup topic or based on your pin assignment setting in the .qsf file. RW You can query this in the Parameter Table Lookup Operation Sequence as described in the Address Lookup topic or based on your pin assignment setting in the .qsf file. RO
[7:0] Reserved 8'hD0 RW 8'hE8 RO
Table 68.  Address Register for Pin Input Delay Feature
Bit Description Avalon® MM Register CSR Register
Value Access Type Value Access Type
[31:28] Reserved 4'h0 RW N/A RO
[27:24] Specify the PHY Lite for Parallel Interfaces IP interface ID.

Depending on the Interface ID parameter in the Parameter Editor.

RW N/A RO
[23:21] Specify the Avalon controller calibration bus base address. 3'h4 RW N/A RO
[20:13] Specify the lane address of an interface. This value is depending on the resource fitting process during compilation. You can query this in the Parameter Table Lookup Operation Sequence as described in the Address Lookup topic. RW N/A RO
[12:9] Reserved 4'hC RW N/A RO
[8:7] Select DQ pin sets to access.
  • 2'h1: DQ 0 to DQ 5
  • 2'h2: DQ 6 to DQ11
RW N/A RO
[6:4] Select the specific DQ pin to access.
  • 3'h0: DQ 0 and DQ 6
  • 3'h1: DQ 1 and DQ 7
  • 3'h2: DQ 2 and DQ 8
  • 3'h3: DQ 3 and DQ 9
  • 3'h4: DQ 4 and DQ 10
  • 3'h5: DQ 5 and DQ 11
RW N/A RO
[3:0] Reserved 4'h0 RW N/A RO
Table 69.  Address Register for Strobe Input Delay Feature
Bit Description Avalon® MM Register CSR Register
Value Access Type Value Access Type
[31:28] Reserved 4'h0 RW N/A RO
[27:24] Specify the PHY Lite for Parallel Interfaces IP interface ID.

Depending on the Interface ID parameter in the Parameter Editor.

RW N/A RO
[23:21] Specify the Avalon controller calibration bus base address. 3'h4 RW N/A RO
[20:13] Specify the lane address of an interface. This value is depending on the resource fitting process during compilation. You can query this in the Parameter Table Lookup Operation Sequence as described in the Address Lookup topic. RW N/A RO
[12:0] Reserved 13'18E0 RW N/A RO
Table 70.  Address Register for Strobe Enable Phase Feature
Bit Description Avalon® MM Register CSR Register
Value Access Type Value Access Type
[31:28] Reserved 4'h0 RW 4'h0 RO
[27:24] Specify the PHY Lite for Parallel Interfaces IP interface ID.

Depending on the Interface ID parameter in the Parameter Editor.

RW

Depending on the Interface ID parameter in the Parameter Editor.

RO
[23:21] Specify the Avalon controller calibration bus base address. 3'h4 RW 3'h4 RO
[20:13] Specify the lane address of an interface. This value is depending on the resource fitting process during compilation. You can query this in the Parameter Table Lookup Operation Sequence as described in the Address Lookup topic. RW You can query this in the Parameter Table Lookup Operation Sequence as described in the Address Lookup topic. RO
[12:0] Reserved 13h'18F0 RW

13'h1998

RO
Table 71.  Address Register for Strobe Enable Delay Feature
Bit Description Avalon® MM Register CSR Register
Value Access Type Value Access Type
[31:28] Reserved 4'h0 RW 4'h0 RO
[27:24] Specify the PHY Lite for Parallel Interfaces IP interface ID.

Depending on the Interface ID parameter in the Parameter Editor.

RW

Depending on the Interface ID parameter in the Parameter Editor.

RO
[23:21] Specify the Avalon controller calibration bus base address. 3'h4 RW 3'h4 RO
[20:13] Specify the lane address of an interface. This value is depending on the resource fitting process during compilation. You can query this in the Parameter Table Lookup Operation Sequence as described in the Address Lookup topic. RW You can query this in the Parameter Table Lookup Operation Sequence as described in the Address Lookup topic. RO
[12:0] Reserved 13'h1808 RW

13'h19A8

RO
Table 72.  Address Register for Read Valid Delay Feature
Bit Description Avalon® MM Register CSR Register
Value Access Type Value Access Type
[31:28] Reserved 4'h0 RW 4'h0 RO
[27:24] Specify the PHY Lite for Parallel Interfaces IP interface ID.

Depending on the Interface ID parameter in the Parameter Editor.

RW

Depending on the Interface ID parameter in the Parameter Editor.

RO
[23:21] Specify the Avalon controller calibration bus base address. 3'h4 RW 3'h4 RO
[20:13] Specify the lane address of an interface. This value is depending on the resource fitting process during compilation. You can query this in the Parameter Table Lookup Operation Sequence as described in the Address Lookup topic. RW You can query this in the Parameter Table Lookup Operation Sequence as described in the Address Lookup topic. RO
[12:0] Reserved 13'h180C RW

13'h19A4

RO

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