PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 6/21/2022

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Document Table of Contents Address Lookup

If you do not set the pin locations in the .qsf file, the lane addresses and pin placement to an interface changes every time you compile your design in Intel® Quartus® Prime software. However, the PHY Lite for Parallel Interfaces IP is always generated as if the IP is the only IP in a column, with lane addresses starting from 0. You need to determine the lane and pin addresses in order to dynamically reconfigure the calibration settings in the IP core.

Figure 68. Lane and Pin Placement Dependent AddressesThis figure shows two examples of a placed group with two lanes, 16 data pins and a differential strobe.

To provide a unified way to look up reconfigurable feature addresses for a specific interface both before and after placement, the address information is stored in memory in the I/O column. This memory is addressable over the same Avalon memory-mapped interface used for feature reconfiguration.

You can cache lookups 1 to 4 (8-bytes of information) to have pin and lane translations in one look-up.

Table 64.  Memory Lookup ComponentsThis table lists the two main components of the memory lookup.
Component Description
Global parameter table Stores pointers to the individual interface parameter tables. The global parameter table lists all interfaces in the column (both the External Memory Interfaces and PHY Lite for Parallel Interfaces IP).
Set of individual interface parameter tables Contain interface specific information. This is where pin-level and lane-level address look-ups are performed.
Figure 69. Memory Overview in Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices

Below are the steps to determine the lane and pin addresses from the lookup tables (the sequence corresponds to the sequence in the preceding figure. ):

Table 65.  Parameter Table Lookup Operation SequenceThe base address for PHY Lite for Parallel Interfaces Intel® Arria® 10 and PHY Lite for Parallel Interfaces Intel® Cyclone® 10 GX FPGA IP are 24'h00E000.
Legend in Memory Overview in Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices Description
1 Search for Interface Parameter Table in Global Parameter Table (cache once per interface)
  • {id{3:0],24'h00E000} + 28'h18 to {id{3:0],24'h00E0000} + 28'h2C
  • 1 to 11 look-ups
2 Retrieve number of groups in the interface (cache once per interface)
  • {id[3:0],24'h00E000} + {4'h0,pt_ptr[23:0]} + 4'h4
  • You can skip this sequence if the number of groups is saved in the core during compilation (for example, hard coded in RTL logic)
3 Retrieve group information (cache once per group)
  • {id[3:0],24'h00E000} + {4'h0,pt_ptr[23:0]} + 24'h4 + grp_num
  • Not always necessary
4 Retrieve Lane/Pin Address Offsets for group (cache once per group)
  • {id[3:0],24'h00E000} + pt_ptr + {22'd0,num_grps[7:2],2'b00} + 28'd8
5 Perform lane/pin address translation (cache once per pin)
  • {id[3:0],24'h00E000} + {12'h000,lane_ptr[15:0]} + lane_num
  • {id[3:0],24'h00E000} + {12'h000,pin_ptr[15:0]} + {17'h0,pin_num[5:0], 1'b0}
6 Read/Write Avalon Calibration Bus
  • {id[3:0],24'h800000} + read_from_step_4 + intra_lane_addr