PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 6/21/2022
Public
Document Table of Contents

4.4.1.1. Calibrated VREF Settings

Table 87.  Calibrated VREF SettingsThis table lists the calibrated VREF settings that you can set over the Avalon memory-mapped calibration bus. This table is applicable to all Intel FPGA devices.
avl_writedata[5:0] % of VCCIO
000000 60.00%
000001 60.64%
000010 61.28%
000011 61.92%
000100 62.56%
000101 63.20%
000110 63.84%
000111 64.48%
001000 65.12%
001001 65.76%
001010 66.40%
001011 67.04%
001100 67.68%
001101 68.32%
001110 68.96%
001111 69.60%
010000 70.24%
010001 70.88%
010010 71.52%
010011 72.16%
010100 72.80%
010101 73.44%
010110 74.08%
010111 74.72%
011000 75.36%
011001 76.00%
011010 76.64%
011011 77.28%
011100 77.92%
011101 78.56%
011110 79.20%
011111 79.84%
100000 80.48%
100001 81.12%
100010 81.76%
100011 82.40%
100100 83.04%
100101 83.68%
100110 84.32%
100111 84.96%
101000 85.60%
101001 86.24%
101010 86.88%
101011 87.52%
101100 88.16%
101101 88.80%
101110 89.44%
101111 90.08%
110000 90.72%
110001 91.36%
110010 92.00%
110011 -> 111111 Reserved

Did you find the information on this page useful?

Characters remaining:

Feedback Message