PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 6/21/2022
Public
Document Table of Contents

4.2.1. Top Level Interfaces

The PHY Lite for Parallel Interfaces IP consists of the following ports:

  • Clocks and reset
  • Core data and control (divided into input and output paths)
  • I/O (divided into input and output paths)
  • Avalon memory-mapped configuration bus (available only when Dynamic Reconfiguration feature is enabled)
Figure 58. Top-Level Interface This figure shows the top-level diagram of the PHY Lite for Parallel Interfaces IP interface.

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