PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 6/21/2022
Public
Document Table of Contents

2.2.4.2.1. Control Registers Addresses

For the PHY Lite for Parallel Interfaces Intel® Agilex™ FPGA IP, the address register map is automatically generated when the IP is generated. The address register map can be obtained in the ip/ed_synth/<PHY Lite IP folder>/altera_arch_fm_xxx/synth/addr_map.vh.

Table 8.  Control Register Addresses Description
Feature Bit Description
Pin Output Delay [26:24] The Avalon® controller calibration bus base address. Value is fixed to 3’h3.
[23:21] Reserved with value 3’h0.
[20:13] The lane address of an interface.
[12:8] The address for the physical location of a pin within a lane.
[7:0] Reserved with value 8’d0
Pin Input Delay [26:24] The Avalon® controller calibration bus base address. Value is fixed to 3’h3.
[23:21] Reserved with value 3’h0.
[20:13] The lane address of an interface.
[12:9] Reserved with value 4’hC.
[8:7]

DQ pin sets to access.

  • 2'h1: DQ 0 to DQ 5
  • 2'h2: DQ 6 to DQ11
[6:4]

Specific DQ pin to access.

  • 3'h0: DQ 0 and DQ 6
  • 3'h1: DQ 1 and DQ 7
  • 3'h2: DQ 2 and DQ 8
  • 3'h3: DQ 3 and DQ 9
  • 3'h4: DQ 4 and DQ 10
  • 3'h5: DQ 5 and DQ 11
[3:0] Reserved with value 4’h0.
Strobe Input Delay [26:24] The Avalon® controller calibration bus base address. Value is fixed to 3’h3.
[23:21] Reserved with value 3’h0.
[20:13] The lane address of an interface.
[12:0] Reserved with value 13'h18E0.
Strobe Enable Phase [26:24] The Avalon® controller calibration bus base address. Value is fixed to 3’h3.
[23:21] Reserved with value 3’h0.
[20:13] The lane address of an interface.
[12:0] Reserved with value 13'h18F0.
Strobe Enable Delay [26:24] The Avalon® controller calibration bus base address. Value is fixed to 3’h3.
[23:21] Reserved with value 3’h0.
[20:13] The lane address of an interface.
[12:0] Reserved with value 13'h1808.
Read Valid Delay [26:24] The Avalon® controller calibration bus base address. Value is fixed to 3’h3.
[23:21] Reserved with value 3’h0.
[20:13] The lane address of an interface.
[12:0] Reserved with value 13'h180C.

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