126.96.36.199. Output Path
The output path consists of a FIFO and an interpolator. As described in the following figure, data coming from the core together with relative enable signals are written into the Write FIFO synchronously with phy_clk. The VCO clock generates the interpolator_clk which is used to generate the desired output delay.
|Write FIFO||Serializes the output data from the core with a serialization factor of up to 8 (in DDR quarter-rate).|
|Interpolator||Works with the FIFO block to generate the desired output delay.|
The group_<n>_strobe_out / group_<n>strobe_io is restricted to the following patterns:
- Tristate before and after data capture.
- Toggling for data capture.
In a case where group_<n>_strobe_out / group_<n>strobe_io requires different patterns than the patterns stated above, replace the dedicated strobe pins with data pins.
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