PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 6/21/2022
Public
Document Table of Contents

4.2.5.2.2. Parameter Table Examples

Single PHY Lite for Parallel Interfaces Intel® Arria® 10 and Intel® Cyclone® 10 GX FPGA IP

The following figure shows an example of the design containing a single PHY Lite for Parallel Interfaces Intel® Arria® 10 and Intel® Cyclone® 10 GX FPGA IPs with one bidirectional group composed of four data bits and one strobe. Refer to the Example of Identifying the Lane and Pin Addresses from Parameter Table to determine the lane and pin addresses from the parameter table.

Figure 70. Parameter Table Example for Single PHY Lite IP Core 0
Table 66.  Example of Identifying the Lane and Pin Addresses from Parameter Table
Step Address Address Value Data Description
To access the parameter table. Base address 24’hE000
To determine the size of the parameter table by generating an address. Base address + 24’h014 24’hE000 + 24’h014= 24’hE014 00000064 The size of the parameter table is 7C that means the information about PHY Lite is from address 24’hE000 to 24’hE064.
To determine the address offset of PHY Lite in the parameter table. Base address + 24h’018 24’hE000 + 24h’018 = 24h’018 80000044
  • Bit[1:0]: 44 address offset point to PHY Lite IP
  • {4’h0, pt_ptr[23:0]} is 044
  • Bit[6]: PHY Lite interface ID
To determine the number of groups in PHY Lite for interfaces. Base address + {4’h0, pt_ptr[23:0]} + 4’h4 24’hE000 + 24’h044 + 4’h4 = 24’hE048 00000001 1 indicates the number of groups in this PHY Lite.
To determine the group information that the number of lanes and number of pins. Base address + {4’h0, pt_ptr[23:0]} + 4’h8 24’hE000 + 24’h044 + 4’h8 = 24’hE04C 00000005
  • Bit[5:0]: num_pins[5:0] represents 5 pins
  • Bit[7:6]: num_lanes[7:6] represents 1 lane
To determine lane offset and pin offset. Base address + 24’h048 + 24’h08 24’hE000 + 24’h048 + 24’h08 = 24’h E050 00540058
  • Bit[3:0]: pin_off[15:0] = pin_off = 058
  • Bit[7:4]: lane_off[31:16] = lane_off = 054
  • Lane_ptr = 054 and pin_ptr = 058
To determine the lane address. Base address + {12'h000lane_ptr[15:0]} 24’hE000 +24’h054 = 24’hE054 00000000 Lane address is 0x00
To determine the pin address at 24’hE058 to 24’hE064. Base address +{12'h000,pin_ptr[15:0]} 24’hE000 + 24’h058 = 24’hE058 00F100E0
  • Bit[3:0]: strobe_io = lane 0x00, pin 0
  • Bit[7:4]: data_io[0] = lane 0x00, pin 1
24’hE05C 00F300F2
  • Bit[3:0]: data_io[1] = lane 0x00, pin 2
  • Bit[7:4]: data_io[2] = lane 0x00, pin 3
24’hE060 000000F4 Bit[3:0]: data_io[3] = lane 0x00, pin 4
24’hE064 00000000 End of the address
Note: {lane_addr[7:0], 0xE, pin[3:0]} for strobe and {lane_addr[7:0], 0xF, pin[3:0]} for data.

Two PHY Lite for Parallel Interfaces Intel® Arria® 10 and Intel® Cyclone® 10 GX FPGA IPs

The following figure shows an example of a design containing two PHY Lite for Parallel Interfaces Intel® Arria® 10 and Intel® Cyclone® 10 GX FPGA IPs, each with one bidirectional group composed of four data bits and one strobe. Both interfaces are in the same I/O column, and therefore must merge the tables.

Figure 71. Parameter Table Example for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices


Important: There is no guarantee of ordering the interface parameter tables in the merged table. You must perform a search to locate a specific interface parameter.

For more information about the contents of the parameter table, refer to the Address Lookup topic.

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