PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 6/21/2022
Public
Document Table of Contents

2.5.2. Reference Clock

You are recommended to source the reference clock to the PHY Lite for Parallel Interfaces Intel® Agilex™ FPGA IP from a dedicated clock pin. Use the clock pin in the I/O sub-bank with the following command:
set_location_assignment <PIN_NUMBER> -to <pll_ref_clock_signal_name>

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