3.5.2. Reference Clock
You are recommended to source the reference clock to the PHY Lite for Parallel Interfaces IP from a dedicated clock pin. Use the clock pin in one of the I/O banks used by the PHY Lite for Parallel Interfaces IP. You must use contiguous I/O banks to implement multiple interfaces (consisting of a combination of External Memory Interface and PHY Lite for Parallel Interfaces IPs). If you use the same reference clock for these interfaces, place the reference clock in any of the contiguous I/O banks.
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