PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 6/21/2022
Document Table of Contents Internal FPGA Path Timing Violation

If timing violations are reported at the internal FPGA paths (such as <instance_name>_usr_clk or <instance_name>_phy_clk_*), consider the following guidelines:

If setup time violation is reported, lower the clock rate of the user logic from full-rate to half-rate, or from half-rate to quarter-rate. This reduces the frequency requirement of the IP core-to-core data transfer.

If hold time violation is observed, you may increase hold uncertainty value to equal or higher than the violation amount in the .sdc file. This will provide a more stringent constraint during design fitting. Following is an example to increase the hold uncertainty.
If {$::quartus(nameofexecutable) != “quartus_sta”}{

	set_clock_uncertainty -from [<instance_name>_phy_clk_*] -to [<instance_name>_phy_clk_*] -hold 0.3 -add

	set_clock_uncertainty -from [<instance_name>_usr_clk] -to [<instance_name>_usr_clk] -hold 0.3 -add


However, increasing the hold uncertainty value may cause setup timing violation at slow corner.

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