PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 6/21/2022

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4.5.3. Reset

You can source the reset to the PHY Lite for Parallel Interfaces IP from an external pin or from the core. If you source the reset from an external pin, you must configure the I/O standard of the reset signal in the .qsf file with the following command:
set_location_asignment <PIN_NUMBER> -to <signal_name>