184.108.40.206. Dynamic Reconfiguration Guidelines
The PHY Lite for Parallel Interfaces Intel® Agilex™ FPGA IP allows you to dynamically reconfigure the features of the interface. No traffic should occur during reconfiguration. Reframing is necessary, particularly in continuous strobe mode of operation. Intel recommends performing dynamic calibration for application with core clock frequency of more than 533 MHz and/or using ×36 DQS trees. This section provides the general guidelines for calibrating Intel® Agilex™ I/O architecture.