PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

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ID 683716
Date 6/21/2022
Public
Document Table of Contents

2.2.4.3. Dynamic Reconfiguration Guidelines

The PHY Lite for Parallel Interfaces Intel® Agilex™ FPGA IP allows you to dynamically reconfigure the features of the interface. No traffic should occur during reconfiguration. Reframing is necessary, particularly in continuous strobe mode of operation. Intel recommends performing dynamic calibration for application with core clock frequency of more than 533 MHz and/or using ×36 DQS trees. This section provides the general guidelines for calibrating Intel® Agilex™ I/O architecture.

Note: Follow the guidelines when generating your own dynamic reconfiguration controller.

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