PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 6/21/2022
Public
Document Table of Contents

4.3.2.5. Termination Signals

Table 83.  Termination SignalsThe termination signals are signals that are available when you enable the Expose termination ports parameter.
Signal Name Direction Width Description
group_seriesterminationcontrol Input

16

Connect this signal to the series termination control signal of the OCT Intel® FPGA IP to receive series termination code to calibrate Rs.
group_parallelterminationcontrol Input

16

Connect this signal to the parallel termination control signal of the OCT Intel® FPGA IP to receive parallel termination code to calibrate Rt.

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