PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

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ID 683716
Date 6/21/2022
Public
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3.6.1.2.1. Dynamic Reconfiguration Using Finite State Machine

This design example is a simulation design example that is capable to perform dynamic calibration for PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP.

Features

  • Perform dynamic reconfiguration using Avalon controller
  • Read and write transactions monitoring
  • Delay values monitoring

Software Requirements

  • Intel® Quartus® Prime software
  • Active-HDL, ModelSim* - Intel® FPGA Edition, or VCS Simulator

Functional Description

This design example introduces the cfg_ctrl and avl_ctrl blocks, which work with the sim_ctrl module to demonstrate the basic functionality of the PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP Avalon memory-mapped based reconfiguration. The agent is also modified to insert delays on the data and clocks, which the new modules will compensate for.

NOTE: The cfg_ctrl module performs a simplistic reconfiguration of the interface that stops at the first working delay values. The design example only support simulation. A robust calibration algorithm should sweep over the entire valid range of delays to choose the correct value for the application.

Figure 53. Dynamic Reconfiguration Using Finite State Machine Design ExampleThis figure shows a high-level view of the simulation design example with one group.


Table 55.  Design Components Description
Component Description
ref_clk_gen Generates clock to reset_gen, PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP ADDR/CMD (ref_clk), and PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP (ref_clk) blocks.
reset_gen Generates reset to PHY Lite for Parallel Interfaces ADDR/CMD and PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP blocks.
sim_ctrl
  • Generates read/write commands to PHY Lite for Parallel Interfaces ADDR/CMD block.
  • Generates side read/write commands and data to Agent block.
  • Generates strobe and data to Driver block.
Driver Generates strobe and data for each group and to PHY Lite for Parallel Interfaces_ Intel® Stratix® 10 FPGA IP block.
PHY Lite for Parallel Interfaces ADDR/CMD Passing read/write commands and command clock from sim_ctrl to Agent.
Agent FIFO to store data from PHY Lite for Parallel Interfaces DUT and side read/write data from sim_ctrl block.
cfg_ctrl

This is configuration control block which performs read and write delay calibration before test begin.

The calibration results is passed to the PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP through Avalon Controller.

Contains 4 FSMs:

  1. Main FSM – cfg_ctrl state
  2. Write Strobe FSM – Calibration state for Output Strobe
  3. Read Strobe FSM – Calibration state for Input Strobe
  4. Read Enable FSM – Calibration state for Strobe Enable and Input Data
avl_ctrl

The Avalon controller is used to perform address translation to store delay settings from the calibration done by cfg_ctrl block.

Figure 54. Design Example Functional Flow

Generate the Dynamic Reconfiguration with Configuration Control Module Design Example

  1. In Intel® Quartus® Prime software, instantiate PHY Lite for Parallel Interfaces IP core.
  2. Customize parameter settings per your requirement and turn on the Use dynamic reconfiguration option.
  3. Click Generate Example Design. Specify a directory name to generate the design example.
  4. To generate Verilog or mixed-language simulation files, go to the design example directory and run the following script in Nios II Command Shell.
    quartus_sh -t make_sim_design.tcl VERILOG
  5. To generate VHDL simulation files, go to the design example directory and run the following script in Nios II Command Shell.
    quartus_sh -t make_sim_design.tcl VHDL

Run the Dynamic Reconfiguration with Configuration Control Design Example

Follow these steps to compile and simulate the design:

  1. Change the working directory to <Example Design>\sim\ed_sim\sim\<Simulator> .
  2. Run the simulation script for the simulator of your choice. Refer to the table below.
    Simulator Working Directory Steps
    Modelsim <Example Design>\sim\ed_sim\sim\mentor
    1. do msim_setup.tcl
    2. ld_debug
    3. Add desired signals into the waveform window.
    4. run -all
    VCS <Example Design>\sim\ed_sim\sim\synopsys\vcs
    1. sh vcs_setup.sh
    VCSMX <Example Design>\sim\ed_sim\sim\synopsys\vcsmx
    1. sh vcsmx_setup.sh
    Aldec Example Design\sim\ed_sim\sim\aldec
    1. do rivierapro_setup.tcl
    2. ld_debug
    3. Add desired signals into the waveform window.
    4. run -all
Figure 55. Sample of Simulation Output

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