PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 6/21/2022
Public
Document Table of Contents

2.4.2. On-Chip Termination (OCT)

PHY Lite for Parallel Interfaces Intel® Agilex™ FPGA IP provides valid OCT settings for each group (refer to I/O Standards). These settings are written to the .qip of the instance during generation. If you select an I/O standard that supports OCT in the General tab, you can use the OCT blocks provided in the Intel® Agilex™ devices.

You can instantiate the OCT block in one of two ways:

  • Using RZQ_GROUP assignment in the assignment editor, or
  • Manual insertion of OCT block

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