126.96.36.199. Clock and Reset Interface Signals
|ref_clk||Input||1||Reference clock for the PLL. The reference clock must be synchronous with strobe_in to ensure the dqs_enable signal is in-sync with strobe_in.|
|reset_n||Input||1||Resets the interface. This signal is asynchronous.|
|interface_locked||Output||1||Interface locked signal from PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP to core logic. This signal indicates that the PLL and PHY circuitry are locked.
Data transfer should starts after the assertion of this signal.
|core_clk_out||Output||1|| Use this core clock in the core-to-periphery transfer of soft logic data and control signals.
The core_clk_out frequency depends on the interface frequency and clock rate of user logic parameter.
|pll_extra_clock[0..3]||Output||4||These are the additional output clock signals generated by PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP when you enable Specify additional output clocks based on existing PLL parameter.|
|pll_locked||Output||1||This is the locked signal for the additional output clocks generated by the IP.|
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