PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

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ID 683716
Date 6/21/2022
Public
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4.5.4. Constraining Multiple PHY Lite for Parallel Interfaces to One I/O Bank

You can instantiate multiple PHY Lite for Parallel Interfaces Intel FPGA IPs within an I/O column. To constrain groups from separate PHY Lite for Parallel Interfaces IP instances into the same I/O bank, the instances must share the same reference clock and reset sources, the same external memory frequencies and the same voltage settings.

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