Due to the limitation of the PHY Lite for Parallel Interfaces Intel® FPGA IP, you may see the error message above if you have more than one PHY Lite for Parallel Interfaces Intel FPGA IP place in the same I/O bank.
Device Family: Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10
Intel Software: Quartus Prime Pro, Quartus Prime Standard
Last Modified: March 17, 2021
Version Found: v19.3
Bug ID: 1507413021