Device Family: Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10

Intel Software: Quartus Prime Pro, Quartus Prime Standard

Type: Answers

Area: Tools


Last Modified: March 17, 2021
Version Found: v19.3
Bug ID: 1507413021

Error(14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 PHYLITE_GROUP(s)).

Description

Due to the limitation of the PHY Lite for Parallel Interfaces Intel® FPGA IP, you may see the error message above if you have more than one PHY Lite for Parallel Interfaces Intel FPGA IP place in the same I/O bank.

Workaround/Fix

To work around this problem, avoid placing more than one PHY Lite for Parallel Interfaces Intel® FPGA IP place in the same I/O bank. This is because each of the PHY Lite for Parallel Interfaces Intel FPGA IP has a specific interface requirement which required a specific PLL setting. However, there is only one PLL available in a given bank.