PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 6/21/2022
Public
Document Table of Contents

3.2.5.1. RTL Connectivity

The PHY Lite for Parallel Interfaces IP exposes the Avalon memory-mapped master and Avalon memory-mapped slave interfaces when you enable the dynamic reconfiguration feature. If the generated IP is the only PHY Lite for Parallel Interfaces IP (with dynamic reconfiguration) or External Memory Interface IP in the I/O column, connect only the Avalon memory-mapped slave interface with a master in the core. Otherwise, connect Avalon memory-mapped master and slave interfaces as described in the following section.

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