PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

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ID 683716
Date 6/21/2022
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4.3.2.1. Clock and Reset Interface Signals

Table 78.  Clock and Reset Interface Signals
Signal Name Direction Width Description
ref_clk Input 1 Reference clock for the PLL. The reference clock must be synchronous with strobe_in to ensure the dqs_enable signal is in-sync with strobe_in.
reset_n Input 1 Resets the interface. This signal is asynchronous.
interface_locked Output 1 Interface locked signal from PHY Lite for Parallel Interfaces IP to Intel FPGA core. This signal indicates that the PLL and PHY circuitry are locked.

Data transfer should starts after the assertion of this signal.

core_clk_out Output 1 Use this core clock in the core-to-periphery transfer of soft logic data and control signals.

The core_clk_out frequency depends on the interface frequency and clock rate of user logic parameter.

pll_extra_clock[0..3] Output 4 These are the additional output clock signals generated by PHY Lite for Parallel Interfaces IP when you enable Specify additional output clocks based on existing PLL parameter.
Important: PHY Lite for Parallel Interfaces in Intel® Arria® 10 and Intel® Cyclone® 10 GX devices do not support exposing additional output clocks when VCO frequency is below 600 MHz.
pll_locked Output 1 This is the locked signal for the additional output clocks generated by the IP.

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