PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

Download
ID 683716
Date 6/21/2022
Public
Document Table of Contents

2.2.3. PHY Lite for Parallel Interfaces Intel® Agilex™ FPGA IP Top Level Interfaces

The PHY Lite for Parallel Interfaces Intel® Agilex™ FPGA IP consists of the following ports:

  • Clocks and reset
  • Core data and control (divided into input and output paths)
  • I/O (divided into input and output paths)
Figure 9. Top-Level Interface This figure shows the top-level diagram of the PHY Lite for Parallel Interfaces Intel® Agilex™ FPGA IP interface.

Did you find the information on this page useful?

Characters remaining:

Feedback Message