PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

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ID 683716
Date 6/21/2022
Public
Document Table of Contents

3.5.5. Dynamic Reconfiguration

Dynamic reconfiguration reconfigures the input and output delays in the PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP core.

You can perform real-time configuration on the delay of DQS/strobe or DQ/data signals. This feature maximizes the data valid window, allowing the design to achieve timing closure at high frequency. You can turn on Use dynamic reconfiguration in the parameter editor of the PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP core in the Intel® Quartus® Prime Pro Edition software.

The reconfiguration is performed via the Avalon® memory-mapped interface. Multiple IP cores requiring Avalon® core access require daisy chain connectivity.

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