PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

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ID 683716
Date 6/21/2022
Public
Document Table of Contents

4.7. Application Specific Design Example

This design example demonstrates the PHY Lite for Parallel Interfaces IP implementation for a NAND Flash design in Intel® Arria® 10 devices.

The following figure shows the RTL view of the design example.

Figure 90.  RTL Viewer for a NAND Flash Simple Design Based on the PHY Lite for Parallel Interfaces IP

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