PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 6/21/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents Output and Strobe Enable Minimum and Maximum Phase Settings

When dynamically reconfiguring the interpolator phase settings, the values must be kept within the ranges below to ensure proper operation of the circuitry.

Table 74.  Output and Strobe Enable Minimum and Maximum Phase Settings
VCO Multiplication Factor Core Rate Minimum Interpolator Phase Maximum Interpolator Phase
    Output Bidirectional Bidirectional with OCT Enabled  
1 Full 0x080 0x100 0x100 0xA80
Half 0x080 0x100 0x100 0xBC0
Quarter 0x080 0x100 0x100 0xA00
2 Full 0x080 0x100 0x180 0x1400
Half 0x080 0x100 0x180 0x1400
Quarter 0x080 0x100 0x180 0x1400
4 Full 0x080 0x100 0x280 0x1FFF
Half 0x080 0x100 0x280 0x1FFF
Quarter 0x080 0x100 0x280 0x1FFF
8 Full 0x080 0x100 0x480 0x1FFF
Half 0x080 0x100 0x480 0x1FFF
Quarter 0x080 0x100 0x480 0x1FFF

For more information about performing various clocking and delay calculations, depending on the interface frequency and rate, refer to PHYLite_delay_calculations.xlsx.