Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.1, you might see the above compilation error in the Questa*-Intel® FPGA Edition Software version 2022.1 while running a simulation of the VHDL-based design example of the PHY Lite for Parallel Interfaces Intel® Agilex™ FPGA IP. This is due to the PHYLITE IP Tester with PRBS Generator and Check contained within the design example that uses the port "channel_strobe_out_in", which is no longer used in the PHY Lite for Parallel Interfaces Intel® Agilex™ FPGA IP.
To work around this problem, suppress the error by replacing line 127 in the msim_setup.tcl as follow:
set USER_DEFINED_ELAB_OPTIONS "-suppress 1130, 14408, 16154"
This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software v22.2.