Article ID: 000089901 Content Type: Troubleshooting Last Reviewed: 06/21/2022

Error (Suppressible): ../../ip/ed_sim/ed_sim_tester_0/sim/ed_sim_tester_0.vhd(93): (vopt-1130) port "channel_strobe_out_in" of entity "phylite_tester" is not in the component being instantiated

Environment

  • Intel® Quartus® Prime Pro Edition
  • Questa*-Intel® FPGA Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.1, you might see the above compilation error in the Questa*-Intel® FPGA Edition Software version 2022.1 while running a simulation of the VHDL-based design example of the PHY Lite for Parallel Interfaces Intel® Agilex™ FPGA IP. This is due to the PHYLITE IP Tester with PRBS Generator and Check contained within the design example that uses the port "channel_strobe_out_in", which is no longer used in the PHY Lite for Parallel Interfaces Intel® Agilex™ FPGA IP.

    Resolution

    To work around this problem, suppress the error by replacing line 127 in the msim_setup.tcl as follow:

    set USER_DEFINED_ELAB_OPTIONS "-suppress 1130, 14408, 16154" 

     

    This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software v22.2.

    Related Products

    This article applies to 1 products

    Intel® Agilex™ 7 FPGAs and SoC FPGAs

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