E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs
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Ixiasoft
2.9.11. Ethernet Adaptation Flow with Non-external AIB Clocking
Refer to Loading a PMA Configuration and PMA Registers 0x200 to 0x203 Usage sections in the E-tile Transceiver PHY User Guide for more details on the adaptation flow and how to get started.
This adaptation flow assumes a valid Ethernet traffic.
- Assert i_sl_tx_rst_n/i_tx_rst_n/soft_tx_rst and i_sl_rx_rst_n/i_rx_rst_n/soft_rx_rst signals.
- Trigger PMA analog reset. 18 19
- Reload PMA settings (call the PMA attribute sequencer) on all lanes.
- Apply control status registers (CSR) reset.
- For 100GE/25GE/10GE single instance, cycle control status registers (CSR) reset.
- For 25GE/10GE multilane instance, hold CSR reset on slave channels, cycle master channel CSR reset, then release CSR reset on slave channels as indicated in the below figure.
Figure 33. Reset Sequence in 10G/25G Multilane Mode
- Deassert the i_sl_tx_rst_n/i_tx_rst_n/soft_tx_rst signal.
- If using a PMA configuration, load the PMA configuration using control status registers (CSR). This is loaded to the registers using PMA registers 0x200 to 0x203 20.
- Write 0x40143 = 0x80.
- Read 0x40144[0] until it changes to 1.
- Enable internal serial loopback 21 and run initial adaptation. Verify that the initial adaptation status is complete using interrupt code 0x0126 and data 0x0B00.
- Enable mission mode and disable internal serial loopback (skip this step if using internal serial loopback)21.
- Wait for valid data traffic on RX and then proceed to the next step.
- Run initial adaptation. Verify that the initial adaptation status is complete using interrupt code 0x0126 and data 0x0B00 (skip this step if using internal serial loopback).
- Run continuous adaptation 22.
- Deassert the i_sl_rx_rst_n/i_rx_rst_n/soft_rx_rst signal.
- Optional: Verify that the link status signal rx_aligned transitions high.
- Send packets.