E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 12/28/2022

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Document Table of Contents

3.9.1. CPRI PHY Functional Blocks

The E-Tile CPRI PHY Intel FPGA IP consists of the following modules:
  • Native PHY—E-tile transceiver channels which consists of PMA and RS-FEC hard logic to support CPRI and Ethernet protocols. The native PHY also contains the following block:
    • 64b/66b Decoder: A hard PCS block within the Native PHY that provides encoding scheme for 10.1376, 12.1651 and 24.33024 Gbps CPRI line rates.
  • Soft reset sequencer—A reset sequencer that staggers and asserts digital reset signals according to the E-Tile CPRI PHY Intel FPGA IP requirements.
  • Elastic FIFO (EFIFO)—A dual clock FIFO that match the rate differences between the E-tile hard logic and soft logic.
  • Latency measurement—A module that generates sync pulse to measure the datapath delay of the E-Tile CPRI PHY Intel FPGA IP.
  • Reconfiguration and Control Status Register (CSR) address decoder—This is an address decoder for PHY reconfiguration interface and soft CSR.
  • 8b/10b Decoder: A soft PCS block that provides encoding scheme for 2.4/3.0/4.9/6.14/9.8 CPRI line rates.