E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 9/26/2022
Public
Document Table of Contents

2.11.17.1. Asynchronous Adapter Clock in 10G/25G Mode

When enabling asynchronous adapter clocks, you may clock the TX/RX interface in TX MAC Interface to User Logic using the i_sl_async_clk_tx/rx clock asynchronous to the i_sl_sync_clk_tx/rx signals used in the internal IP datapath.

Note: In 10G mode, the asynchronous adapter clock is available only when PTP is enabled.
Figure 57. Clock Connection in Asynchronous FIFO Operation
Table 60.  Supported Clock Rates for MAC Client Asynchronous FIFO Operation in 25G ModeThe below rates assume 1 byte IPG and disabled preamble-pass-through.
Rate Clock Rate
Min i_sl_async_clk_tx Max i_sl_async_clk_tx Min i_sl_async_clk_rx Max i_sl_async_clk_rx
10G 32/25G

390.625 MHz

402.83203215 MHz

390.625 MHz

402.83203215 MHz

31 When Asynchronous mode is disabled, i_sl_clk_tx/rx signals drive both, TX/RX interface and TX/RX datapath in 25G mode.
32 In 10G mode, the asynchronous adapter clock is available only when PTP is enabled.

Did you find the information on this page useful?

Characters remaining:

Feedback Message