E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 9/26/2022
Public
Document Table of Contents

3.10.3. RX MII Interface

Table 97.  CPRI PHY RX MII Interface
Port Name Width Domain Description
o_sl_rx_mii_d[n] 64 per channel o_rx_clkout2[n]

RX MII data. Data is in MII encoding. o_sl_rx_mii_d[7:0] holds the first byte the IP core received on the Ethernet link. o_sl_rx_mii_d[0] holds the first bit the IP core received on the Ethernet link.

o_sl_rx_mii_c[n] 8 per channel o_rx_clkout2[n] RX MII control bits. Each bit corresponds to a byte of RX MII data. o_sl_rx_mii_c[0] corresponds to o_sl_rx_mii_d[7:0], o_sl_rx_mii_c[1] corresponds to o_sl_rx_mii_d[15:8], and so on.

If the value of a bit is 1, the corresponding data byte is a control byte. If the value of a bit is 0, the corresponding data byte is data.

The Start of Packet byte (0xFB) and End of Packet byte (0xFD) are control bytes.

Figure 91. Receiving Data Using the RX MII Interface

The figure above shows how to read packets from the RX MII interface.

  • The packets are MII encoded.
    • Each byte in o_sl_rx_mii_d has a corresponding bit in o_sl_rx_mii_c that indicates whether the byte is a control byte or a data byte; for example, o_sl_rx_mii_c[2] is the control bit for o_sl_rx_mii_d[23:16].
  • The byte order for the RX MII interface flows from right to left; the first byte that the core receives is o_sl_rx_mii_d[7:0].
  • The first bit that the core receives is o_sl_rx_mii_d[0].

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