E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 9/26/2022
Public
Document Table of Contents

2.12.5.17. Pause Quanta 1

Offset: 0x621

Pause Quanta Fields

Bit Name Description Access Reset
15:0 pause_quanta Pause quanta
16b value specifying the Quanta value transmitted in XOFF frames
  • The Quanta value indicates to the remote link partner the amount of time to apply flow control
  • 1 Quanta corresponds to 512 bit times.
    • On a 10Gx1 or 25Gx1 link, 512 bit times is 8 valid clock cycles
    • On a 100Gx4 link, 512 bit times is 2 valid clock cycles
  • Minimum allowed value: 1
  • Maximum value: 16'hFFFF
  • The default value for quanta is 16'hFFFF. Using the max value simplifies the use of flow control by making it directly controlled by XON and XOFF, and reduces the bandwidth required for retransmitted control frames
  • After power-up, pause_quanta is set to the default value (16'hFFFF)
  • After i_csr_rst_n, pause_quanta is set to the value given by the module parameter pause_quanta for PAUSE, and pfc_pause_quanta_n for PFC
RW 0xFFFF

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