E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 9/26/2022
Public
Document Table of Contents

2.4.1. Simulation Environment

Intel performs the following tests on the E-Tile Hard IP for Ethernet Intel FPGA IP in the simulation environment using internal and third party standard bus functional models (BFM):

  • Constrained random tests that cover randomized frame size and contents
  • Randomized error injection tests that inject Frame Check Sequence (FCS) field errors, runt packets, and corrupt control characters, and then check for the proper response from the IP core
  • Assertion based tests to confirm proper behavior of the IP core with respect to the specification
  • Extensive coverage of our runtime configuration space and proper behavior in all possible modes of operation

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