E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 9/26/2022
Public
Document Table of Contents

3.10.2. TX MII Interface

Table 96.  CPRI PHY TX MII Interface
Port Name Width Domain Description
i_sl_tx_mii_d[n] 64 bits per channel o_tx_clkout2[n]

TX MII data. Data must be in MII encoding. i_sl_tx_mii_d[7:0] holds the first byte the IP core transmits on the Ethernet link. i_sl_tx_mii_d[0] holds the first bit the IP core transmits on the Ethernet link.

i_sl_tx_mii_c[n] 8 bits per channel o_tx_clkout2[n] TX MII control bits. Each bit corresponds to a byte of the TX MII data signal. For example, i_tx_mii_c[0] corresponds to i_tx_mii_d[7:0], i_tx_mii_c[1] corresponds to i_tx_mii_d[15:8], and so on.

If the value of a bit is 1, the corresponding data byte is a control byte. If the value of a bit is 0, the corresponding data byte is data.

The Start of Packet byte (0xFB) and End of Packet byte (0xFD) are control bytes.

Figure 90. Transmitting Data Using TX MII Interface

The figure above shows how to write packets directly to the TX MII interface.

  • The packets are written using MII.
    • Each byte in i_sl_tx_mii_d has a corresponding bit in i_sl_tx_mii_c that indicates whether the byte is a control byte or a data byte; for example, i_sl_tx_mii_c[1] is the control bit for i_sl_tx_mii_d[15:8].
  • The byte order for the TX MII interface flows from right to left; the first byte to be transmitted from the interface is i_sl_tx_mii_d[7:0].
  • The first bit to be transmitted from the interface is i_sl_tx_mii_d[0].

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