E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 9/26/2022
Public
Document Table of Contents

2.12.5.15. TX Flow Control Feature Configuration

Offset: 0x611

txsfc_ehip_cfg Fields

Bit Name Description Access Reset
1 en_pfc Enable Priority Flow Control TX
1: Enable Priority Flow Control
  • This feature requires the TX MAC
  • Enabling this feature allows the TX MAC to transmit PFC frames when requested, even if the flow of data through the datapath is inhibited
  • The TX datapath must be reset after changing this field
  • To shut off TX PFC without resetting the datapath, use tx_pause_en
  • To request the transmission of PFC frames through AVMM, use tx_pause_request
  • After power-on, this reset is set to 0
  • After i_csr_rst_n, this register is set to a value given by the module parameter flow_control
RW 0x0
0 en_sfc Enable Standard Flow Control TX
1:Enable Standard Flow Control (link PAUSE)
  • This feature requires the TX MAC
  • Enabling this feature allows the TX MAC to transmit PAUSE frames when requested, even if the flow of data through the datapath is inhibited
  • The TX datapath must be reset after changing this field
  • To shut off TX PAUSE without resetting the datapath, use tx_pause_en
  • To request the transmission of PAUSE frames through AVMM, use tx_pause_request
  • After power-on, this reset is set to 0
  • After i_csr_rst_n, this register is set to a value given by the module parameter flow_control
RW 0x0

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