E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

ID 683468
Date 12/28/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2.7.4.1. Channel Placement

Depending on the number of bonded PMA channels, the Channel Placement tool supports two E-tile variants, 24-channel placement and 16-channel placement variant.

In Intel® Stratix® 10 devices, each E-tile provides Hard IP for up to 4 100G Ethernet channels, and up to 24 10G/25G Ethernet channels. In Intel® Agilex™ devices, each E-tile provides Hard IP for up to 4 100G Ethernet channels, and either up to 24 10G/25G Ethernet channels in 24-channel bonding configuration, or up to 16 10G/24G Ethernet channels in 16-channel bonding configuration.

Figure 10. Ethernet Hard IP Overview

The figure shows an example placement of the channels using the E-tile Channel Placement Tool.

RS-FEC is configurable for single-lane 10G/25G and multi-lane 100G Ethernet interfaces.

Figure 11. Ethernet Cores Position on an E-tile Device

You can place the core by constraining a serial pin from the core to one of the transceiver pins on the selected E-tile device. For example, if you constrain the serial pins from a Variant A core to transceiver pin 10, the core is placed in Variant A position 10.